Analog and Digital Filter Design for Precision ADC Signal Chains

Filtering in a precision ADC system must satisfy frequency-domain rejection, input settling, and response-time requirements together. Analog filters determine which disturbances reach the converter, while digital filters control bandwidth and decimation after sampling. Both must be designed around the ADC input structure, channel switching, and system error budget to realize the converter's performance.

Instrumentation, process control, motor control, and power-line relay protection all depend on precision acquisition. The source discusses SAR ADCs with resolutions of 18 bits or more at several MSPS, and 24-bit or 32-bit sigma-delta ADCs at hundreds of kSPS. The focus here is low-pass filtering for first-Nyquist-zone operation, rather than a filter synthesis procedure.

1 Assigning the analog and digital roles

An ideal low-pass response has a flat passband, infinite stopband attenuation, and an instantaneous transition. Real filters introduce passband loss or ripple, finite out-of-band rejection, and phase or group delay. Their response shapes therefore affect amplitude accuracy, noise, and time-domain behavior differently.

Figure 1 Analog and digital filtering within a data acquisition chain

Figure 2 Ideal low-pass response compared with practical filter families

Analog filtering acts before conversion. It attenuates high frequency noise and interference before they alias into the signal band and reduces the risk of modulator saturation from out-of-band overdrive or noise spikes. Current limiting and attenuation also provide some input protection. Digital filtering cannot recover information already lost through saturation or aliasing.

Digital filtering acts after conversion. It can reduce out-of-band input noise and contributions from supplies, references, interface feedthrough, on-chip thermal noise, and quantization in the sampled data. It is readily configurable, but introduces latency and can only process information that has already been sampled. Table 1 compares the main characteristics.

Table 1 System characteristics of analog and digital filtering

2 Making input RC settling the first constraint

An antialiasing filter must precede the ADC. Its task is to preserve the required passband accuracy while reducing components that could fold into that band. The ADC input impedance and sampling capacitor interact with the network, so the RC filter cannot be treated as an isolated circuit.

The AD7980 example uses a 16-bit, 1 MSPS SAR ADC with an 18.9 Ω external resistor and 2.7 nF capacitor, giving a cutoff near 3.11 MHz. Figure 3 also specifies 710 ns conversion time, 290 ns acquisition time, and a 27 pF sampling capacitor. For a 100 kHz input, 3.11 MHz may appear unnecessarily wide, but the short acquisition window imposes a settling requirement.

Figure 3 AD7980 input RC network and acquisition timing constraints

Increasing the resistor to 590 Ω lowers the cutoff to approximately 100 kHz. This improves out-of-band rejection but attenuates a signal near 100 kHz by about 30% and slows settling. The internal sample-and-hold capacitor may then fail to reach the required accuracy during acquisition. Narrower bandwidth does not necessarily improve the conversion result.

Verify settling of the complete input network within the available acquisition time. This is especially important for ADCs with substantial input current, low equivalent input impedance, or unbuffered sigma-delta inputs. A narrow low-pass filter can instead be placed before a high input impedance amplifier. A high input impedance converter is another option; the source cites 500 MΩ for the ADAS3022.

3 Checking throughput and phase in multichannel systems

A multiplexer can switch between negative and positive full scale, producing a step across the entire input span. If the channels share a filter after the multiplexer, that filter must settle to a new value after every switch. The arrangement reduces component count and cost but limits throughput.

Figure 4 Per-channel and shared filtering in a multiplexed acquisition chain

Individual filters before the multiplexer can reduce the repeated settling penalty of a shared filter, at the expense of additional components and cost. The choice should reflect both switching-time and per-channel cost requirements.

Simultaneously sampled channels also require phase matching. Frequency-dependent filter phase can be described through group delay; nonconstant group delay spreads waveforms in time and degrades pulse response. Motor phase-current measurement and power-line monitoring should include channel-to-channel phase error and its temperature dependence in the error budget.

4 Selecting filter order and components for the application

Strong interference near the edge of the first Nyquist zone favors a steep roll-off. Increasing order can narrow the transition and improve preservation of the desired passband, but raises sensitivity to component and gain matching. Added resistors, amplifiers, and other elements also introduce in-band noise, so order alone is not the design objective.

Figure 5 Butterworth filter order and transition-band steepness

In an AD7606 relay-protection example, the signals of interest include a 50 Hz or 60 Hz fundamental and its first five harmonics. Protection channels have lower accuracy requirements than measurement channels and can use a first-order RC filter. Measurement channels can use a second-order arrangement for improved passband behavior and roll-off. The two functions need not use identical filters.

Low distortion also depends on component nonlinearity. Besides selecting a low THD+N amplifier, consider resistor voltage and power coefficients and capacitor dielectric. Thin-film or metal resistor technologies are options for high performance chains. Where cost permits, polystyrene and NP0/C0G ceramic capacitors are candidates for low distortion filtering.

Resistor thermal noise depends on resistance and bandwidth. A simple RC low-pass filter has an equivalent noise bandwidth of 1/(4RC). Substitution into the thermal noise equation gives the familiar kBT/C expression for integrated noise across the capacitor. Increasing resistance alone therefore does not establish that integrated noise rises without considering the bandwidth change.

vn,rms = √(4kBTRB)

B = 1/(4RC), giving vn,rms = √(kBT/C)

Here kB = 1.38065 × 10⁻²³ J/K, T is absolute temperature, and B is equivalent brick-wall noise bandwidth. Figure 6 compares capacitors on EVAL-AD7960FMCZ with a 10 kHz sinusoidal input. C76 and C77 are both 1 nF in 0603 packages, using NP0 in one test and X7R in the other. The original plots show THD of approximately −117.11 dB and −66.65 dB, demonstrating that equal nominal capacitance and package size do not imply equal distortion.

Figure 6a Spectrum with 1 nF 0603 NP0 capacitors

Figure 6b Spectrum with 1 nF 0603 X7R capacitors

Once accuracy, bandwidth, and component constraints are established, an analog filter design tool can calculate resistor and capacitor values and assist amplifier selection. The source mentions the ADI Analog Filter Wizard; its results still require verification against input settling and nonlinearity constraints.

5 Predicting oversampling gains from actual noise

At a higher sampling rate, digital filtering can first restrict the signal bandwidth and then decimate to the required output rate. This reduces in-band quantization noise and relaxes the analog antialiasing transition requirement, at the cost of a faster ADC and more digital processing.

Figure 7 Digital band limiting after oversampling reduces in-band quantization noise

For an ideal N-bit ADC limited only by quantization noise, SNR follows the expression below. OSR is the oversampling ratio, fs is sample rate, and BW is the desired bandwidth. The formula is not a guaranteed result for a practical system.

SNR = 6.02N + 1.76 + 10 log10(OSR) dB

OSR = fs/(2BW)

A real chain also contains source noise, component thermal noise, shot noise, supply and reference noise, digital feedthrough, and phase noise associated with clock jitter. Some contributions have low frequency flicker characteristics. Practical improvement is consequently often lower than a quantization-only model predicts.

In the EVAL-AD7960FMCZ measurements described in application note AN-1279, the 18-bit AD7960 reaches about 123 dB dynamic range with 256× oversampling. The measured improvement is approximately 1 dB to 2 dB below theory, attributed in the source mainly to low frequency signal-chain noise. Such high dynamic range acquisition is useful in spectroscopy, MRI, gas chromatography, vibration, oil and gas exploration, and seismic measurements.

Figure 8a Dynamic range measurement without oversampling processing

Figure 8b Approximately 123 dB dynamic range with 256× oversampling

6 Budgeting latency even with integrated digital filters

Digital filtering can run in an FPGA, DSP, or processor, or use functions integrated in the ADC. The AD7606 includes a first-order digital sinc oversampling filter configured through OS pins. The AD7175-x offers sinc3, sinc5 + sinc1, and enhanced 50 Hz/60 Hz rejection filters. The AD7124-x provides fast-settling modes using sinc4 + sinc1 or sinc3 + sinc1.

Filter order and master clock affect latency, so real-time control must check the full interval from an input change to a valid result. A datasheet's continuous output data rate generally describes steady operation on one channel. After switching channels, the modulator and filter must settle and remove the previous channel's influence from the filter state. Effective multiplexed throughput may therefore be several times lower than the continuous rate.

Optimized filters reduce this delay. The source cites the AD7175-x sinc5 + sinc1 filter, which provides single-cycle settling at output rates of 10 kSPS and below for multiplexed acquisition. Continuous output rate and valid-result rate after switching should still be distinguished.

7 Meeting the antialiasing requirement before decimation

Oversampling simplifies analog filtering but does not make the decimated output inherently alias-free. Before reducing output rate, components above the new Nyquist frequency must be sufficiently attenuated. Analog and digital filtering should jointly make the retained bandwidth compatible with the final rate.

The EVAL-AD7606, EVAL-AD7607, and EVAL-AD7608EDZ platforms can operate at 200 kSPS per channel. The source test uses OSR = 32, producing a 6.25 kSPS output. Applying a 3.5 kHz, −6 dBFS sinusoid to the AD7606 produces an image near −10 dBFS at 2.75 kHz, consistent with 6.25 − 3.5 = 2.75 kHz. In this example, the digital filter's rejection alone is insufficient to prevent that disturbance from folding after decimation.

Figure 9 A 2.75 kHz alias after decimation to 6.25 kSPS

A suitable analog antialiasing network is still required, along with a check of digital decimation-filter attenuation at possible interference frequencies. Final design decisions should cover settling, amplitude and phase error, component noise, distortion, latency, and final sample bandwidth, together with implementation cost and resources.