TC7SZ00FU,LJ(CT
Toshiba Semiconductor and StorageJapan

TC7SZ00FU,LJ(CT

ActiveGates and InvertersUSV

IC GATE NAND 1CH 2-INP USV

TC7SZ00FU,LJ(CT is a CMOS 2-input NAND gate with 1.65-5.5V supply, 2.4ns typical propagation delay, USV package, and AEC-Q100 compliance.Checked against the datasheet

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Technical parameters

Key specs

Logic typeNAND
Elements1
Inputs2
Supply voltage1.65 ~ 5.5 V
Propagation delay4.3 nsMax · 5V

Datasheet-verified parameters

22 items
ParameterValue and test conditionsSource
Logic Type2-Input NAND Gate
Units1
Inputs2
Supply Voltage1.65 to 5.5 V
Propagation Delay2.4 ns (typ.) at VCC = 5.0 V, CL = 50 pF
PackageUSV
Operating Temperature-40 to 125 °C
GradeAEC-Q100 (Rev. H)
High-level Input VoltageVCC × 0.75 (Min) for VCC = 2.3 to 5.5 V
Low-level Input VoltageVCC × 0.25 (Max) for VCC = 2.3 to 5.5 V
High-level Output Voltage2.3 V (Min) at VCC = 3.0 V, IOH = -24 mA
Low-level Output Voltage0.55 V (Max) at VCC = 3.0 V, IOL = 24 mA
Input Leakage Current±1.0 μA (Max) at VIN = 5.5 V or GND, VCC = 0 to 5.5 V
Quiescent Supply Current2 μA (Max) at VIN = VCC or GND, VCC = 5.5 V
Supply Voltage (Absolute Max)-0.5 to 6.0 V
Input Voltage (Absolute Max)-0.5 to 6.0 V
DC Output Current (Absolute Max)±50 mA
Power Dissipation (Absolute Max)200 mW
Storage Temperature-65 to 150 °C
Input Rise and Fall Time0 to 5 ns/V at VCC = 5.0 ± 0.5 V
5.5 V Tolerant InputsYes
5.5 V Power Down Protection OutputYes
All parameters (19)ExpandCollapse
Power
Current - Output High, Low32mA, 32mA
Current - Quiescent (Max)2 µA
Voltage - Supply1.8V ~ 5.5V
AC and DC characteristics
Max Propagation Delay @ V, Max CL4.3ns @ 5V, 50pF
Environment and package
Mounting TypeSurface Mount
Operating Temperature-40°C~85°C
PackageTape & Reel (TR); Cut Tape (CT); Digi-Reel®
Package / Case5-TSSOP, SC-70-5, SOT-353
Supplier Device Package5-SSOP
Other
Base Product Number7SZ00
Features-
Input Logic Level - High-
Input Logic Level - Low-
Logic TypeNAND Gate
MfrToshiba Semiconductor and Storage
Number of Circuits1
Number of Inputs2
Product StatusActive
SeriesTC7SZ

Pinout and package

Pin Assignment (Top view)
Pin Assignment (Top view)
Package: USV
PinNameFunctionSource
1INB (Input B)
2INA (Input A)
3GND(Ground)
4OUTY (Output Y)
5VCC(Supply)

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DatasheetDatasheet · 131.0 KB · 2026-11-03
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