Si5518Q

NetSync™ Low Phase Noise Jitter Attenuating Clock for 5G/eCPRI/SyncE/IEEE

All alternatives

AC and DC characteristics
Input Frequency Max (MHz)	1000
Input Frequency Min (MHz)	0.0000005
Line Impedance Match	0
Loop Bandwidth Max (MHz)	0.004
Loop Bandwidth Min (MHz)	0.000000001
Output Frequency Domains	3
Output Frequency Max	3200
Output Frequency Min	0.0000005
Xtal Input Frequency	54
Environment and package
Automotive Grade	false
Package Size (mm)	10x10
Package Type	QFN72
Temperature Range Max (°C)	95
Temperature Range Min (°C)	-40
Other
4G/LTE Wireless Clocks	true
56G SerDes	false
5G Clocks	true
AccuTime™ Supported	true
Clock Generators	false
Clock outputs	18
Control	SPI
Description	Network Sync & JA Clock for IEEE 1588v2/SyncE with JESD204B/C
DSPLLs	4
Intel x86 Clocks	false
Jitter Attenuating Clocks	true
Jitter Recommended Range (fs)	<=100
OPN	TBD
Ouput Format(s)	LVDS, S-LVDS, AC coupled LVPECL, LVCMOS, HCSL, CML
Output Format Categories	Differential; Single-Ended
PCI Express	false
Phase Jitter (ps RMS)	0.047
Real Time Clock	false
Reference Inputs	6
Reference Type	External
Spread Spectrum	false
Standards Compliance	ITU-T G.8273.2 (T-TSC, T-BC), ITU-T G.8273.4 (T-BC-P, T-BC-A, T-TSC-P, T-TSC-A), G.8262 (EEC Options 1 and 2), G.8262.1 (eEEC), and G.8273.1 (T-GM)
Synchronous Ethernet/1588	true
VDDO (V)	1.8; 2.5; 3.3
VDD (V)	1.8; 3.3
Wireline or Wireless Application	Wireless
XTAL Input	true