Texas InstrumentsUnited States
IC ETH PHY 10/100MBPS 48-LQFP
DP83848IVVX is a 10/100 Mb/s Ethernet physical layer transceiver in LQFP-48 package, operating from -40°C to 85°C, supporting MII/RMII interfaces and Auto-MDIX, compliant with IEEE 802.3.Checked against the datasheet
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Technical parameters
Datasheet-verified parameters
18 items| Parameter | Value and test conditions | Source |
|---|---|---|
| Package | LQFP (PT) 48 | |
| Operating Temperature | -40 to 85 °C | |
| Grade | Industrial | |
| RoHS | Yes | |
| Supply Voltage | 3.3 V ± 0.3 V | |
| Power Dissipation | 267 mW (Max), < 270 mW (Typ) |
All parameters (7)
| Power | |
|---|---|
| Power Dissipation ( $P_{D}$ ) | 267 mW |
| Supply voltage ( $V_{CC}$ ) | 3.3 V ± 0.3 V |
| Environment and package | |
| Body Size (NOM) | 7.00 mm × 7.00 mm |
| Operating Temperature (Extended) | -40°C to 105°C |
| Package | HLQFP (48) |
| Other | |
| Interface | MII/RMII/SNI |
| Speed | 10/100 Mb/s |
Pinout and package
PackageLQFP (PT) 48
| Pin | Name | Function | Source |
|---|---|---|---|
| 1 | TX_CLK | (Transmit Clock) | |
| 2 | TX_EN | (Transmit Enable) | |
| 3 | TXD_0 | (Transmit Data 0) | |
| 4 | TXD_1 | (Transmit Data 1) | |
| 5 | TXD_2 | (Transmit Data 2) | |
| 6 | TXD_3/SNI_MODE | (Transmit Data 3/SNI Mode) | |
| 7 | PWR_DOWN/INT | (Power Down/Interrupt) | |
| 8 | TCK | (JTAG Clock) | |
| 9 | TDO | (JTAG Data Out) | |
| 10 | TMS | (JTAG Mode Select) | |
| 11 | TRST# | (JTAG Reset) | |
| 12 | TDI | (JTAG Data In) | |
| 13 | RD | - (Receive Differential Negative) | |
| 14 | RD | + (Receive Differential Positive) | |
| 15 | AGND | (Analog Ground) | |
| 16 | TD | - (Transmit Differential Negative) | |
| 17 | TD | + (Transmit Differential Positive) | |
| 18 | PFBIN1 | (Power Feedback Input 1) | |
| 19 | AGND | (Analog Ground) | |
| 20 | RESERVED | (Reserved) | |
| 21 | RESERVED | (Reserved) | |
| 22 | AVDD33 | (Analog Power 3.3V) | |
| 23 | PFBOUT | (Power Feedback Output) | |
| 24 | RBIAS | (Receive Bias Resistor) | |
| 25 | CLK_OUT | (Clock Output) | |
| 26 | LED_ACT/COL/AN_EN | (LED Activity/Collision/Auto-Negotiation Enable) | |
| 27 | LED_SPEED/AN1 | (LED Speed/Auto-Negotiation 1) | |
| 28 | LED_LINK/AN0 | (LED Link/Auto-Negotiation 0) | |
| 29 | RESET_N | (Reset Active Low) | |
| 30 | MDIO | (Management Data Input/Output) | |
| 31 | MDC | (Management Clock) | |
| 32 | IOVDD33 | (IO Power 3.3V) | |
| 33 | X2 | (Crystal 2) | |
| 34 | X1 | (Crystal 1) | |
| 35 | IOGND | (IO Ground) | |
| 36 | DGND | (Digital Ground) | |
| 37 | PFBIN2 | (Power Feedback Input 2) | |
| 38 | RX_CLK | (Receive Clock) | |
| 39 | RX_DV/MII_MODE | (Receive Data Valid/MII Mode) | |
| 40 | CRS/CRS_DV/LED_CFG | (Carrier Sense/Carrier Data Valid/LED Config) | |
| 41 | RX_ER/MDIX_EN | (Receive Error/MDIX Enable) | |
| 42 | COL/PHYAD0 | (Collision/PHY Address 0) | |
| 43 | RXD_0/PHYAD1 | (Receive Data 0/PHY Address 1) | |
| 44 | RXD_1/PHYAD2 | (Receive Data 1/PHY Address 2) | |
| 45 | RXD_2/PHYAD3 | (Receive Data 2/PHY Address 3) | |
| 46 | RXD_3/PHYAD4 | (Receive Data 3/PHY Address 4) | |
| 47 | IOGND | (IO Ground) | |
| 48 | IOVDD33 | (IO Power 3.3V) | |
| 49 | GNDPAD | (Ground Pad) |
Documents
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