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Analog Devices Inc.United States

ADF4001BCPZ-RL

Clock Generators, PLLs, Frequency Synthesizers20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

PLL SYNTHESIZER 200MHz 2.7V-5.5V 20-LFCSP

200 MHz clock generator PLL, 2.7 V to 5.5 V supply, 20-lead LFCSP package, industrial temperature range, featuring low phase noise and programmable charge pump currents.Checked against the datasheet

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Technical parameters

Key specs

Max frequency200 MHzMax
Supply voltage2.7 ~ 5.5 V

Datasheet-verified parameters

23 items
ParameterValue and test conditionsSource
Maximum Frequency200 MHz
Power Supply Voltage2.7 V to 5.5 V
Package20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] (CP-20-6)
Operating Temperature Range-40°C to +85°C
GradeIndustrial (B Version)
RoHS CompliantZ = RoHS Compliant Part
Typical Operating Current4.5 mA
Absolute Maximum Ratings (AVDD to GND)-0.3 V to +7 V
Storage Temperature Range-65°C to +150°C
Maximum Junction Temperature150°C
Charge Pump Power Supply (VP)Greater than or equal to VDD; can be set to 5 V in 3 V systems
Reference Input ThresholdNominal VDD/2
Reference Input DC Resistance100 kΩ
RSET Nominal Voltage0.66 V
Maximum Charge Pump Current (RSET=4.7kΩ)5 mA
RF Input Absolute Maximum Voltage±600 mV
DATA to CLOCK Setup Time10 ns min
DATA to CLOCK Hold Time10 ns min
CLOCK High Duration25 ns min
CLOCK Low Duration25 ns min
CLOCK to LE Setup Time10 ns min
LE Pulsewidth20 ns min
Transistor Count6425 (CMOS) and 50 (Bipolar)
All parameters (6)ExpandCollapse
AC and DC characteristics
Phase Detector Frequency55 MHz max
RF Input Frequency10/200 MHz min/max
Environment and package
Operating Temperature Range-40°C to +85°C
Package20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Other
AVDD2.7/5.5 V min/V max
IDD (AIDD + DIDD)5.5 mA max

Pinout and package

Package20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] (CP-20-6)

PinNameFunctionSource
1CPGND, Charge Pump Ground, ground return path for the charge pump
2AGND, Analog Ground, ground return path of the prescaler
3AGND, Analog Ground, ground return path of the prescaler
4RFINB, Complementary Input to the N counter, must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF
5RFINA, Input to the N counter, small signal input, ac-coupled to the external VCO or VCXO
6AVDD, Analog Power Supply, ranges from 2.7 V to 5.5 V, must have the same value as DVDD
7AVDD, Analog Power Supply, ranges from 2.7 V to 5.5 V, must have the same value as DVDD
8REFIN, Reference Input, CMOS input, nominal threshold of VDD/2, dc equivalent input resistance of 100 kΩ
9DGND, Digital Ground
10DGND, Digital Ground
11CE, Chip Enable, logic low powers down the device and puts the charge pump output into three-state mode, high powers up
12CLK, Serial Clock Input, used to clock in serial data to registers, data latched on CLK rising edge
13DATA, Serial Data Input, loaded MSB first, two LSBs are control bits
14LE, Load Enable, CMOS Input, when high loads shift register data into latches
15MUXOUT, Multiplexer Output, allows access to lock detect, scaled RF, or scaled reference frequency
16DVDD, Digital Power Supply, ranges from 2.7 V to 5.5 V, must be the same value as AVDD
17DVDD, Digital Power Supply, ranges from 2.7 V to 5.5 V, must be the same value as AVDD
18VP, Charge Pump Power Supply, should be greater than or equal to VDD, can be set to 5 V in 3 V systems to drive VCO or VCXO
19RSET, Connecting a resistor between this pin and CPGND sets the maximum charge pump output current, nominal voltage 0.66 V
20CP, Charge Pump Output, when enabled provides ±ICP to the external loop filter, driving external VCO or VCXO
EPEPAD, Exposed Pad, should be connected to AGND

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