Connection Diagram
Fairchild SemiconductorUnited States
SHIFT REG 8-BIT 3-STATE 2V-6V 16-SOIC
8-bit serial-in parallel-out shift register with 3-state output latches, operating voltage 2V-6V, max frequency 30MHz, available in SOIC, SOP, TSSOP, and PDIP packages.Checked against the datasheet
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View full reportTechnical parameters
Datasheet-verified parameters
18 items| Parameter | Value and test conditions | Source |
|---|---|---|
| Package | 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150'' Narrow; 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300'' Wide; 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide; 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide; 16-L | |
| Operating Temperature Range | Min: -40°C, Max: +85°C | |
| Recommended Operating Supply Voltage | Min: 2V, Max: 6V | |
| Absolute Maximum Supply Voltage | -0.5V to +7.0V | |
| Storage Temperature Range | -65°C to +150°C | |
| Quiescent Supply Current | Max: 80 µA (VCC=6.0V, TA=-40 to 85°C) |
All parameters (6)
| Power | |
|---|---|
| DC Output Current, per pin (IOUT) | ±35 mA |
| Maximum Quiescent Supply Current (ICC) | 80 µA (Max) |
| Supply Voltage (VCC) | 2 V (Min) to 6 V (Max) |
| AC and DC characteristics | |
| Maximum Operating Frequency of SCK | 30 MHz (Max) |
| Environment and package | |
| Operating Temperature Range (TA) | -40 °C (Min) to +85 °C (Max) |
| Package Description | 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 |
Pinout and package
Connection Diagram
| Pin | Name | Function | Source |
|---|---|---|---|
| 1 | VCC | (Power Supply) | |
| 2 | QA | (Parallel Output A) | |
| 3 | QB | (Parallel Output B) | |
| 4 | QC | (Parallel Output C) | |
| 5 | QD | (Parallel Output D) | |
| 6 | QE | (Parallel Output E) | |
| 7 | QF | (Parallel Output F) | |
| 8 | QG | (Parallel Output G) | |
| 9 | QH | (Parallel Output H) | |
| 10 | GND | (Ground) | |
| 11 | SCLR | (Shift Register Clear, Active Low) | |
| 12 | SCK | (Shift Clock) | |
| 13 | RCK | (Storage Register Clock) | |
| 14 | SER | (Serial Data Input) | |
| 15 | QH' (Serial Output, for Cascading) | ||
| 16 | G | (Output Enable, Active Low) |
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