Bootstrap and Noise Robustness Design for High Voltage Gate Drivers

Abstract  Monolithic high-voltage drivers simplify half-bridge control, yet the bootstrap supply, gate resistors, and parasitics must be engineered as one system. Too little bootstrap capacitance causes droop and undervoltage; excessive switching speed magnifies ringing and false turn-on; layout inductance couples power-stage transients into the driver. This article develops a workflow from charge budgeting to bench verification.

1 A Bootstrap Supply Must Be Refreshed

The diode and capacitor charge while the low-side device is on or the switch node is low. The stored charge then powers the floating high-side driver. The method is inexpensive, but a long high-side on-time drains charge and makes duty cycle and refresh opportunity part of the power-supply design.

The allowed droop must fit between the minimum VCC, diode drop, required gate voltage, and low-side conduction drop. The maintained gate voltage must also remain above the high-side undervoltage-lockout threshold. Use worst-case supply and temperature values.

2 Size from a Complete Charge Budget

Qtot includes the power-switch gate charge, level-shifter charge, floating-section quiescent current, device and driver leakage, diode leakage, and every current integrated over the high-side on-time. The first-order minimum is CBOOTmin equals Qtot divided by the permitted DeltaVBS.

The Infineon example uses 290 nanocoulombs and 0.4 volts to obtain 725 nanofarads. That calculation does not include every PWM duty-cycle and modulation effect, so the final value needs tolerance, DC-bias, temperature, and refresh margin. A low-ESR ceramic capacitor is strongly recommended for the fast gate-charge demand.

3 The Diode Resistor and Capacitor Form One Charger

A bootstrap resistor limits initial and refresh current, but it also forms a time constant with the capacitor. If resistance is too high, the available low-side interval may not restore charge. Electrolytic ESR can create a charging step; a small ceramic in parallel with a larger storage capacitor is often a useful compromise for long on-time designs.

The diode must withstand the bus-related reverse voltage and recover quickly enough to prevent charge returning to VCC. Forward drop and high-temperature leakage belong in the same worst-case budget.

4 Gate Resistance Trades Loss for Immunity

The turn-on resistor controls gate current, switching time, and switch-node dv dt. The turn-off path must also resist Miller-current induced turn-on. If total turn-off resistance is excessive, dv dt current through the reverse-transfer capacitance can raise the gate above threshold and create cross-conduction.

Separate on and off values with a steering diode when needed. Gate charge, plateau voltage, target transition time, and driver output resistance provide an initial estimate; PCB parasitics and measured waveforms determine the final value.

5 Layout Determines Parasitic Stress

Place VCC VSS and VB VS decoupling directly at driver pins. Minimize each gate-drive loop and its return path. Separate the floating high-voltage area from ground-referenced control circuitry, and avoid placing a ground plane close to a high dv dt floating node.

During validation, observe VBS, gate-emitter voltage, the switch node, and negative excursions at COM or VS with low-inductance probes. Include startup, regenerative current, short-circuit turn-off, and maximum bus voltage. Any clamp still has to respect the absolute maximum ratings of the exact driver and power device.

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