The CT-2001A chip adopts a superscalar ASIC architecture, achieving multithreaded concurrency with latency below 20 nanoseconds. It features an integrated FOC analog computing unit, programmable digital filtering, neural network adaptive control, and an analog IDPU (Integral-Differential Processing Unit). With hardware acceleration, latency is as low as 0.2 nanoseconds (compared to 2.8 nanoseconds in traditional solutions). The chip includes 1MB on-chip Flash, 512KB SRAM, 21 digital communication interfaces, and built-in hardware acceleration engines for over 10 cryptographic algorithms, supporting secure features such as storage encryption, user partition protection, and secure boot.
内核RISC-V
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内核RISC-V
| 电源 | |
|---|---|
| Clock & Power Mgmt | • Two PLLs: PLL_INT0 for CPU, PLL_FRA0 for peripherals with spread spectrum • One built-in LDO |
| 环境与封装 | |
| Size | 10 × 10 × 1.26mm |
| Temperature | -40~1 2 5℃ |
| 其他 | |
| ADC | • Built in two 14 bit ADCs • The highest sampling rate is 2MSPS • Two ADCs multiplex 16 sampling channels • Support hardware 1/2/4/8/16/32 oversampling mode • Support external input reference voltage |
| CPM (Comparator Module) | • Support external input reference voltage • Supports up to two CPMs • Comparison of windows with built-in 12 bit DAC reference |
| CPU | • RISC-V 32-bit dual-core, 540 MHz • RV32IMAFDCP instruction set • L1 I/D-Cache 16KB/16KB • Supports single-cycle Tightly Coupled Memory (TCM), I/D-TCM up to 128 KB + 128 KB configurable • Hardware encoding, single/double-precision floating-point units, integrated DSP instruction set • PMP security protection • Core-local interrupt controller (CLINT) and CLIC |
| EPWM (Enhanced PWM) | • 24 channels, resolution up to 120 ps • 16-bit counter • Up/down/up-down counting modes • PWM supports internal phase synchronization • Dead-time control • Six fault inputs • Support pulse group output function |
| FOC Hardware | • Auto acquisition of ADC/SDFM data • Hardware acceleration for CLARKE/PARK/PID/IPARK/SVPWM • Auto-update EPWM duty cycle • Up to Q24 fixed-point precision |
| GPT Timer | • Four 32-bit GPTs • Output compare signal for interrupt and pin output |
| Interfaces | • One USB FS device • Up to 4 SPI (Master/Slave, QSPI) • Up to 9 UART (16550-compatible, baud rate error <2%) • Up to 4 I2C (7/10-bit addressing, up to 400 Kb/s) • One CAN (CAN2.0A/B, up to 1 Mbps) • Up to two CAN-FD (up to 10 Mbps) |
| Model | CT-2001A |
| On-Chip Storage | • SRAM 512 KB (128 KB + 128 KB configurable as TCM) • Flash 1 MB |
| OPA | • Supports up to four OPAs, with programmable gain • Support source following mode, gain amplification mode, and differential amplification mode |
| Packge | BGA144 |
| Product Name | Robot Control Chip |
| SDFM (Sigma-Delta Interface) | • Supports four SDFM • Support serial input decoding • Support SINC 1/2/3 filters • Support OSR configurable |
| System Boot | • Boot order configurable via eFUSE • Supports USB/UART programming • SiP SPI NOR supports external direct mode programming |
| System Control | Built-in THS temperature sensor, supports high/low temperature alarm and over-temperature reset |
| System Security | • Digital signature secure boot • CE for AES/TDES and SHA/HMAC algorithms • SPI_ENC for SPI NOR online decryption • SID built-in 512-bit eFUSE (64-bit user-defined) • Built-in 256-bit TRNG • JTAG lock/unlock support |
| Typical Applications | • Servo motor driver • BLDC motor driver |
| WDOG Watchdog | • Interrupt and reset, timeout configurable from 1 ms to 37 hours • Pause or continue counting configurable in debug mode • Hardware write protection |
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